To read a datum saved in a non-volatile memory cell, it is common to use a sense amplifier arranged for detecting the programmed or erased state of the memory cell by comparing the value of a current passing through the memory cell with a reference current. The fact that a memory cell is programmed or erased translates into a determined conductivity state of the memory cell, and conventionally corresponds to a determined value of the datum saved, such as 1 for the programmed state and 0 for the erased state for example.
FIG. 1 represents the architecture of a classical sense amplifier SA1. On this figure and in the rest of the present application, PMOS-type transistors are designated by references starting with “TP” and NMOS-type transistors are designated by references starting with “TN.” The sense amplifier SA1 comprises a control stage CTLST1, a read stage RDST1 having a read node RND, and an output stage OUTST having an output SOUT, these stages being electrically powered by a voltage Vcc.
The control stage CTLST1 comprises transistors TP1, TP2, TN1 in series and a transistor TN2 in parallel with the transistor TN1. The transistor TP1 receives at its source the voltage Vcc, at its gate a reference voltage Vref and its drain is connected to the source of the transistor TP2. The transistor TP2 receives at its gate a signal ENABLE and its drain is connected to the drains of the transistors TN1, TN2 the sources of which are grounded. The gate of the transistor TN1 is connected to the read node RND, and the gate of the transistor TN2 receives the signal ENABLE.
The read stage RDST1 comprises a transistor TP3 and a cascode transistor TN3 in series with the transistor TP3. The transistor TP3 receives the voltage Vcc at its source and the voltage Vref at its gate. The drain of the transistor TP3 is connected to the drain of the transistor TN3, at which a voltage VMID1 that is applied to the output stage OUTST appears. The source of the transistor TN3 is connected to the read node RND, at which a voltage VSENSE appears. The gate of the transistor TN3 receives a cascode voltage VC1 taken off at the drain of the transistor TP2 of the control stage. The read stage RDST1 further comprises a precharge transistor TP4 the source of which receives the voltage Vcc, the gate of which receives a precharge control signal PRE and the drain of which is linked to the drain of the transistor TN3.
The output stage OUTST comprises an inverting gate INV receiving the voltage VMID1 at input. The output of this inverting gate is applied to the input of a latch, such as a D-type latch DL for example. The latch DL receives a latch signal LATCH at a control input H, and its output Q forms the output SOUT of the sense amplifier.
The read node RND is here linked to a non-volatile memory cell MCELL of a memory array MA, through a column decoder COLDEC and a bit line BLj. The memory cell comprises a floating-gate transistor FGT the source of which is linked to the ground and the gate of which receives a read voltage Vread during a read phase. The threshold voltage of the transistor FGT depends on its programmed or erased state and the read voltage Vread is chosen between the threshold voltage in the programmed state and the threshold voltage in the erased state. Therefore, when the voltage Vread is applied, the transistor FGT is in a high transmission state if it is in the programmed state (low threshold voltage) or is, on the other hand, in a low transmission state or even off if it is in the erased state (high threshold voltage).
The sense amplifier is inactive when the signal ENABLE is on 1 (Vcc) and the voltage Vref equal to Vcc. The transistor TN2 is then on, the transistor TP2 is off and the drain of the transistor TN1 is linked to the ground. No current is circulating in the control stage CTLST1. The transistors TP1, TP3 are off and no current is circulating in the read stage RDST1.
The reading of the memory cell is preceded by an address decoding phase, performed by the decoder COLDEC, allowing the bit line BLj to be linked to the read node RND.
The reading of the memory cell comprises a phase of precharging the bit line BLj, a phase of reading a datum, and a phase of latching the datum. As of the precharge phase, the voltage Vread is taken to an intermediate value between the threshold voltage of the transistor FGT in the programmed state and the threshold voltage of the transistor FGT in the erased state.
The sense amplifier SA1 is first of all activated by taking the voltage Vref to the value Vc−Vtp, Vtp being the threshold voltage of a PMOS transistor. The transistors TP1, TP3 then operate as current generators and respectively supply currents Ibias and Iref in their respective stages.
The precharge phase is engaged by setting the signals ENABLE and PRE to 0. The transistor TN2 goes off and the transistor TP2 becomes on. The voltage VC1 applied to the gate of the transistor TN3 increases and the latter becomes on. The transistors TP3, TP4 are also on and a precharge current is supplied at the read node RND. The transistor TP4 allows the precharge time to be reduced and, as a result, the overall read time, by supplying a precharge current higher than the one that the transistor TP3 alone could supply. This current allows stray capacitances to be charged that are located in the bit line BLj and the voltage VSENSE to be rapidly taken to a determined value, which is substantially equal to the threshold voltage Vtn of an NMOS transistor. Moreover, the limitation of the voltage VSENSE by the cascode transistor TN3 allows the floating-gate transistor FGT to be protected against a phenomenon called drain stress, which translates into an unintentional injection of charges into the floating gate of the transistor and causes spurious programming of the memory cell.
When the determined value of the voltage VSENSE is reached, the transistor TN1 becomes on. The voltage VC1 drops and stabilizes at a value such that, firstly, the currents in the transistors TP1, TN1 are identical and, secondly, the current supplied by the transistor TN3 to the read node corresponds to the current Icell imposed by the transistor FGT in the bit line.
At the end of the precharge phase, the voltage VMID1 is equal to the voltage Vcc minus the voltage drop in the transistor TP3 and the output of the inverting gate INV is on 0. The cascode control voltage VC1 has a value corresponding to the current Icell required by the memory cell.
The read phase as such starts by resetting the precharge signal PRE to 1 (Vcc), such that the transistor TP4 goes off.
If the transistor FGT is in the programmed state, the current Icell is higher than the current Iref supplied by the transistor TP3 (imposed by Vref). The voltage VMID1 is pulled towards the ground and the output of the inverting gate INV goes to 1. If the transistor FGT is in the erased state, the current Icell is low and lower than the current Iref. The transistor TN3 is in a low transmission state and the voltage VMID1 keeps its initial value close to Vcc, such that the output of the inverting gate remains on 0.
The signal LATCH is then applied to the latch DL and the datum supplied by the inverting gate is latched at the output SOUT of the sense amplifier. The latter is then stopped by resetting the signal ENABLE to 1 and by taking the voltage Vref to Vcc again.
Although this sense amplifier is satisfactory by its simplicity, it has the disadvantage of being sensitive to noise, particularly during the phase of reading a memory cell that is in the erased state. This noise can for example correspond to a spurious signal on the supply voltage Vcc due to a current draw created by the switching of logic circuits.
FIG. 2 shows the appearance of the voltages Vcc, Vref, VMID1, VC1 during the reading of a memory cell in the erased state (transistor FGT in a low transmission state), when the voltage Vcc has a spurious fluctuation taking the shape of a voltage drop C1 followed by a voltage peak P1. Before the occurrence of the voltage drop C1, the sense amplifier SA1 is in a stable state. The transistor TN3 is in a low transmission state. The voltage VSENSE is close to Vtn and the voltage VMID1 is close to Vcc. When the voltage drop C1 occurs, stray capacitances absorb the variations of the voltage Vref and the latter does not follow the very rapid variation of the voltage Vcc, the duration of which is for example in the order of approximately ten nanoseconds. Thus, the difference between the voltages Vref and Vcc decreases and becomes lower than the threshold voltage of the transistors TP1, TP3, which go off. As the transistor TP1 is off, the voltage VC1 drops and the transistor TN3 also goes off. The low current passing through the memory cell MCELL starts to discharge the bit line. Then, when the peak P1 occurs on the voltage Vcc, the difference between the voltages Vref and Vcc increases and the transistors TP1, TP3 rapidly become on. The voltage VC1 increases and exceeds the value it had before the occurrence of the voltage drop. The transistor TN3 becomes on with a gate-source voltage Vgs higher than its initial value, which causes a current draw in the bit line. If the current Icell required by the bit line is higher than the current Iref supplied by the transistor TP3, the voltage VMID1 drops as represented in FIG. 2. As a result, the output of the inverting gate temporarily goes to 1. If the datum is latched at this instant by the latch DL, the result of the read is false.
This risk of false reading is not limited to the example that has just been described. A similar risk exists particularly in the event of a temporary drop in the reference voltage Vref or the voltage VSENSE.